Technical Field of the Invention
The present invention relates to information handling systems and, more particularly, to information handling systems having means for controlling a number of clocks operating at different frequencies.
In modern, very large scale integrated (VLSI) circuit processors, the control of timing of data sampling becomes very complex. In some systems, a processor clock might be operating at a first frequency, a first bus clock may be operating at a second frequency, which may have an integer or fractional frequency relationship to the processor clock, and a third bus may be operating at a third frequency which may have a different integer or fractional frequency relationship to the processor clock.
The problem is compounded by the fact that a particular processor integrated circuit may be used in many different information handling systems where it must interface to other data support systems which may be running at different clock speeds. A second problem relates to the first. This is that data arrival time at a processor input may vary depending on the system clock rate of the processor.
Consider, for example, a prior art system having a clock timing as illustrated in FIG. 1.
For a given processor clock rate, the time during which data input to the processor may be valid could vary greatly depending upon a number of delay factors in the system. For example, in the Prior Art example of FIG. 1, a maximum permissible delay could cause the data valid window to begin after the rise of a second cycle of the processor clock and end sometime after the rise of a third cycle of the processor clock. The data sampling must occur within this data valid window based on the maximum possible delay in the system.
The system must also accommodate the permissible minimum delay in the system data path which could result in a data valid window beginning during a first half cycle of the first cycle of the processor clock and ending during the first half cycle of a second cycle of the processor clock.
As can be seen from FIG. 1, in this set of circumstances, in order for a data sampling point to be within the data valid window for maximum delay as well as the data valid window for minimum delay, the sampling point must occur approximately at the quarter cycle point in the second cycle of the processor clock. At that time, the data valid window under maximum delay and the data valid window under minimum delay would have a portion of the windows overlapping each other.
An attempt to sample data at the rise or fall of the processor clock in either maximum data delay or minimum data delay, does not capture valid data for both maximum and minimum delay situations.
The data sampling problem described above is complicated by systems in which one or more buses operating in conjunction with a processor are operating at integer or fractional clock speed ratios with respect to the processor clock speed. For example, a fractional clock speed ratio of 3:2 or 5:2 between the processor clock and a bus clock results in clocking which varies between processor and buses from cycle to cycle. For example, with a 3:2 clock speed ratio as between the processor clock and the bus clock, if the processor clock is running at 200 megahertz, the bus clock would be running at 133 megahertz, meaning that a five nanosecond cycle time for the processor clock would have to be coordinated with a 7.5 nanosecond bus clock. This results in rising edges of the processor clock and the bus clock being coincident once every three cycles.
An additional system complication may occur as a result of simultaneous switching of clocks. If, for example, two bus clocks, are operating at different ratios with respect to a processor clock, switch at the same time, an unusually high load will occur on the power supply perhaps causing power supply voltage drop.